Extinderea compilatorului LLVM pentru arhitectura RISC-V

Abstract

This thesis aimed to integrate a new builtin function into the LLVM compiler backend for the RISCV architecture, designed to perform a scalar dot product between two integer vectors. The motivation behind this work stemmed from the need to understand in depth the mechanisms of code generation in a modern compiler and to enhance the performance of fundamental operations by directly intervening in the instruction selection process.

The work followed a top-down structure, beginning with an analysis of the LLVM frontend, continuing with the generation of intermediate representations, and culminating in the backend phase where the builtin was effectively introduced. The entire implementation process was detailed, from defining the instruction in .td files and inserting it into the instruction selection DAG, to manually writing the expansion logic in a post-register allocation context. The expansion was implemented directly in RISCVExpandPseudo.cpp, allowing full control over the loop structure and register allocation strategy.

Throughout the project, several comparative tests were conducted between the standard scalar implementation, native loop unrolling, and the newly optimized builtin version. Benchmarks executed on the BeagleV-Fire board demonstrated significant performance improvements, particularly for large vector sizes. The builtin reduced execution time by over 5× at optimization level O0 compared to traditional implementation, and maintained competitive performance even under higher optimization levels such as O2 and O3.

A key aspect of the thesis was the documentation of challenges encountered during the process. Technical obstacles related to cross-compiling under Windows, such as frequent out-of-memory errors or system crashes, were mitigated by switching to a Linux Mint dual-boot environment, which offered faster and more stable builds. Hardware-related issues, including soft-bricking of the BeagleVFire board due to excessive or rapid data transmission, were resolved by interfacing with the board through UART using an adapted Arduino circuit. Additionally, the conceptual challenge of choosing the correct expansion location in the LLVM backend was explored, resulting in a successful implementation.

This project not only demonstrated technical proficiency in modifying the internals of a complex open-source compiler, but also provided an applied understanding of RISC-V architecture, embedded systems integration, and the relationship between generated code and real-world performance. The results highlight the importance of backend-level interventions to achieve fine-grained control over instruction generation, particularly in the context of emerging open architectures and energy efficient computing.

Looking ahead, this work can serve as a foundation for the optimization of other common numeric operations, such as vector summation, matrix multiplication, or Euclidean norm calculations, or even for offloading these operations onto an FPGA to perform computations in parallel with the processor. Furthermore, the implementations and insights gained can be leveraged in future academic laboratories, such as ”Embedded Systems”, providing students with concrete examples of real-world compiler modification and performance analysis.