Universitatea Transilvania din Brasov

Open Access Repository

Arhiva digitală instituțională ce oferă acces deschis la rezultatele cercetării științifice și la resurse pentru educație: teze de doctorat, articole științifice, baze de date, studii, rapoarte, lucrări prezentate la conferințe și alte documente relevante.

Universitatea Transilvania din Brasov Open Access Repository

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Universitatea Transilvania din Brasov

Recent Submissions

Extensie a setului de instrucțiuni RISC-V
(Transilvania University of Brasov, 2025-06-18) Alexandru Pușcașu
This thesis focuses on extending the RISC-V ISA for matrix operations. For the proposed extension, we implemented a tightly-coupled accelerator, by using a standard extension interface called CV-X-IF. The accelerator is implemented at RTL in SystemVerilog. The accelerator incorporates a bidimensional memory, which is optimized for matrices accesses, the implemented memory allows access of multiple data in parallel. The bidimensional memory allows us to access multiple data on same row or same column. An important feature is software defined matrix registers; this improves flexibility for programmers. For matrix operations, we will use optimized hardware topology. The defined instructions are on SIMD type. This approach reduces code size and the number of committed instructions, which improve runtime. The new instructions allow defining a matrix, memory operations and matrix operations. Supported matrix operations are addition, subtraction, cross and dot product. Moreover, the accelerator supports matrix-scalar operations, these operations allow scale to scale one matrix. The proposed intrusions have compiler support on RISC-V C toolchain. The compiler support is at assembler level. To evaluate the proposed solution, we analyzed two kinds of metrics: we measured optimization against a simple RISC-V core and FPGA metrics. For those tests we implemented a test environment which included: a RISC-V core, the accelerator, a crossbar and RAM. For the performance tests, we implemented a C benchmark which measures runtime for various matrix operations on both accelerator and RISC-V core. The accelerator is more than 68$\times$ times faster. For matrix multiplication we implemented a systolic array, enhanced for GEMM, and reach more than 2000$\times$ improvement in runtime. On the FPGA side, we could achieve more than 190MHz for our accelerator.
Extinderea compilatorului LLVM pentru arhitectura RISC-V
(Transilvania University of Brasov, 2025-07-02) Vlad-Mihai Popescu
This thesis aimed to integrate a new builtin function into the LLVM compiler backend for the RISCV architecture, designed to perform a scalar dot product between two integer vectors. The motivation behind this work stemmed from the need to understand in depth the mechanisms of code generation in a modern compiler and to enhance the performance of fundamental operations by directly intervening in the instruction selection process. The work followed a top-down structure, beginning with an analysis of the LLVM frontend, continuing with the generation of intermediate representations, and culminating in the backend phase where the builtin was effectively introduced. The entire implementation process was detailed, from defining the instruction in .td files and inserting it into the instruction selection DAG, to manually writing the expansion logic in a post-register allocation context. The expansion was implemented directly in RISCVExpandPseudo.cpp, allowing full control over the loop structure and register allocation strategy. Throughout the project, several comparative tests were conducted between the standard scalar implementation, native loop unrolling, and the newly optimized builtin version. Benchmarks executed on the BeagleV-Fire board demonstrated significant performance improvements, particularly for large vector sizes. The builtin reduced execution time by over 5× at optimization level O0 compared to traditional implementation, and maintained competitive performance even under higher optimization levels such as O2 and O3. A key aspect of the thesis was the documentation of challenges encountered during the process. Technical obstacles related to cross-compiling under Windows, such as frequent out-of-memory errors or system crashes, were mitigated by switching to a Linux Mint dual-boot environment, which offered faster and more stable builds. Hardware-related issues, including soft-bricking of the BeagleVFire board due to excessive or rapid data transmission, were resolved by interfacing with the board through UART using an adapted Arduino circuit. Additionally, the conceptual challenge of choosing the correct expansion location in the LLVM backend was explored, resulting in a successful implementation. This project not only demonstrated technical proficiency in modifying the internals of a complex open-source compiler, but also provided an applied understanding of RISC-V architecture, embedded systems integration, and the relationship between generated code and real-world performance. The results highlight the importance of backend-level interventions to achieve fine-grained control over instruction generation, particularly in the context of emerging open architectures and energy efficient computing. Looking ahead, this work can serve as a foundation for the optimization of other common numeric operations, such as vector summation, matrix multiplication, or Euclidean norm calculations, or even for offloading these operations onto an FPGA to perform computations in parallel with the processor. Furthermore, the implementations and insights gained can be leveraged in future academic laboratories, such as ”Embedded Systems”, providing students with concrete examples of real-world compiler modification and performance analysis.
Accelerarea Hardware a conversiei spațiilor de culoare YUV-RGB pe procesoarele RISC-V
(Transilvania University of Brasov, 2025-07-02) Mariana-Luciana Mitu
This project involved the implementation and analysis of a hardware-software system designed to convert images from the YUV 4:2:2 format into the RGB 8:8:8 format. The system was developed using the BeagleV®-Fire development board, featuring a RISC-V processor and reconfigurable FPGA logic. Four distinct implementations of the conversion algorithm were approached and compared: a purely software approach executed on the processor and three hardware approaches implemented on the FPGA. The hardware implementations evolved gradually, starting with a simplified initial version based on the APB protocol, followed by an optimized version with an internal buffer, and culminating with an advanced implementation that utilizes a DMA Controller for direct and continuous memory access on the FPGA, concurrently employing AXI and APB protocols. The implementation of execution on the processor proved faster in the context of the used platform. However, this advantage does not necessarily reflect the superiority of the software architecture but rather the limitations imposed by the development board’s resources, particularly the bandwidth and clock frequency of the processor-FPGA communication bus. In on-board testing, data transfer via APB at 125 MHz introduces significant overhead, favoring the software solution where the RISC-V processor at 625 MHz can quickly fetch, convert, and write data to memory without the penalties of hardware communication. The project highlights the importance of reconfigurable logic in accelerating computationally intensive tasks, provided that the hardware platform has relevant resources in terms of parallel processing, bandwidth, and processor-FPGA communication. Additionally, the project emphasizes the relevance and importance of exploring RISC-V architectures in the academic environment, contributing to skill development and a deeper understanding of hardware-software interactions in complex embedded systems.
Determining power training needs using the force-velocity profile (imbalance) in elite female volleyball using different vertical jump
(Balneo and PRM Research Journal, 2025-06-25) Joksimović Marko; Badau Dana; Tawfeeq Rebaz B.; Eler Nebahat; Muntean Raul Ioan; Badau Adela; Plevnik Matej
This study aimed to evaluate the Force-Velocity (Fv) profile of elite female volleyball players during the Squat Jump and Countermovement Jump to define the Fv profile of female athletes based on strength, power, and individual mechanical characteristics. The goal was to enhance training efficiency and improve performance in ballistic movements. For this study, we recruited 12 elite female volleyball players from the Montenegro U19 national team. The Fv profile was assessed in two types of muscle contractions: the Squat Jump (concentric contraction) and the Countermovement Jump (eccentric-concentric contraction) to determine Fv imbalance. First, the height of the jump was measured in the Squat Jump, followed by the Countermovement Jump. After that, the Fv profile was analyzed under both contraction types to assess potential imbalances. The results showed an Fv imbalance of 24.93% during the concentric muscle contraction and 29.71% during the eccentric-concentric muscle contraction. Based on these findings, it is suggested that training should prioritize enhancing strength capabilities while simultaneously addressing Fv imbalances. Reducing theoretical Fv imbalance could serve as a supplementary component of training to improve overall physical performance.
Relative Age Effect (RAE) According to Norm Values on Anthropometric Performance and Physical Fitness in 9–11-Year-Old Children
(Journal of Functional Morphology and Kinesiology, 2025-01-14) Kryeziu Artan; Begu Bujar; Badau Dana; Iseni Astrit
Objectives: The main purpose of this study is to identify the relative effect of age (RAE) according to norm values on the anthropometric performance and physical fitness of children between the ages of 9 and 11 years. The data, namely the percentiles of anthropometric parameters and physical fitness, are relevant for identifying the RAE in relation to gender and the month of birth in children. Methods: For the sample in this study, 1185 young people from Kosovo were enrolled, including 626 males and 559 females aged 9–11 years. The gathered data were assessed via the EUROFIT methodology, which takes into account comparisons based on the quartile of birth and the relative age effect (RAE). Results: The results of the data show us that there are significant differences in the RAE among children born in Q2 at the age of 9 years, especially in boys, as well as significant differences in the height variable at the <0.005 significance level. Others factors did not show significant differences, for example, variables that are indicators of physical fitness. For both boys and girls born in Q1, significant differences were mainly found in the indicators of explosive strength, flexibility, static strength, speed, and agility, with a level of significance of p < 0.001, while other indicators did not show significant differences. In addition, there was a significant difference the ratio between genders at the p < 0.001 and p < 0.005 levels, mainly among those born in Q1 and Q2. Similarly, at 10 years of age, children who were born earlier in the year had better scores, although the large disparities were more noticeable between quartiles than between genders, where the significant differences were mainly in the indicators of explosive strength, speed, and strength at the p < 0.001 level, as well as static strength, agility, and speed at the p < 0.005 level. Significant differences were also found for the indicators in terms of gender. At the age of 11, significant percentiles were mainly found in the quartiles at the beginning of the year for both boys and girls, and significant differences were also found at the p < 0.001 level for RAE between quartiles and gender. Conclusions: By using these data, it will be possible to highlight how males, who have demonstrated notable advantages in anthropometric and physical fitness measures, as well as those born in the first few months of the year, exhibit a relative age effect (RAE) in accordance with gender norm values.