Extensie a setului de instrucțiuni RISC-V

Abstract

This thesis focuses on extending the RISC-V ISA for matrix operations. For the proposed extension, we implemented a tightly-coupled accelerator, by using a standard extension interface called CV-X-IF. The accelerator is implemented at RTL in SystemVerilog. The accelerator incorporates a bidimensional memory, which is optimized for matrices accesses, the implemented memory allows access of multiple data in parallel. The bidimensional memory allows us to access multiple data on same row or same column. An important feature is software defined matrix registers; this improves flexibility for programmers. For matrix operations, we will use optimized hardware topology.

The defined instructions are on SIMD type. This approach reduces code size and the number of committed instructions, which improve runtime. The new instructions allow defining a matrix, memory operations and matrix operations. Supported matrix operations are addition, subtraction, cross and dot product. Moreover, the accelerator supports matrix-scalar operations, these operations allow scale to scale one matrix. The proposed intrusions have compiler support on RISC-V C toolchain. The compiler support is at assembler level.

To evaluate the proposed solution, we analyzed two kinds of metrics: we measured optimization against a simple RISC-V core and FPGA metrics. For those tests we implemented a test environment which included: a RISC-V core, the accelerator, a crossbar and RAM. For the performance tests, we implemented a C benchmark which measures runtime for various matrix operations on both accelerator and RISC-V core. The accelerator is more than 68$\times$ times faster. For matrix multiplication we implemented a systolic array, enhanced for GEMM, and reach more than 2000$\times$ improvement in runtime. On the FPGA side, we could achieve more than 190MHz for our accelerator.